The background of the present invention is generally the same as that described in the herein referenced parent application of applicant. The field of the invention pertains to those species of applicant's invention in which analog signal storage and processing is achieved using two independent storage delay lines wherein the storage and processing of alternate segments of the incoming signal occurs respectively in the two delay storage lines with the outputs of the lines combined in alternation to produce a substantially continuous frequency converted output signal. Frequency conversion is affected by storage delay lines of the variable delay type or in the analog shift register version by employing separate and generally unequal read and write clock rates for loading and unloading the two analog shift registers in alternation. The use of this type of storage delay line for frequency conversion can also be incorporated in the various versions of applicant's invention disclosed in the parent application, such as the single delay line versions with or without lagging, gap filling, or speech signal substitution during the reset period for a single line system.